The present targets for the Total and Cold times are:
Total time per SI Mode per measurement: 7600.0 seconds
Fraction of total time the measurement should be cold: 60.0%
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Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 30400 | 60800 | 76000 |
Total Actual Time (secs) | 38868 | 74427 | 96222 |
Delta From Expected (secs) | 8468.00 | 13627.00 | 20222.00 |
% of Expected Total (secs) | 127.86% | 122.41% | 126.61% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 18240.0 | 36480.0 | 45600.0 |
Total Actual Cold Time (secs) | 14848 | 34941 | 36484 |
Delta From Expected (secs) | -3391.08 | -1538.77 | -9115.38 |
% of Exp. Cold Total (secs) | 81.41% | 95.78% | 80.01% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 3 | 29151.00 | 9717.00 |
TE_007AE | 7 | 64710.00 | 9244.29 | |
TE_00B26 | 9 | 86505.00 | 9611.67 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 2 | 19434.00 | 9717.00 |
TE_00CA8 | 1 | 9717.00 | 9717.00 | 4 Chip SI Modes | TE_00C62 | 0 | 0.00 | 0.00 |
III. Statistics Since the Start of the Current Epoch
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 60800 | 68400 | 98800 |
Total Actual Time (secs) | 74560 | 84144 | 124228 |
Delta From Expected (secs) | 13760.00 | 15744.00 | 25428.00 |
% of Expected Total (secs) | 122.63% | 123.02% | 125.74% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 36480.0 | 41040.0 | 59280.0 |
Total Actual Cold Time (secs) | 22315 | 34969 | 45010 |
Delta From Expected (secs) | -14164.72 | -6070.07 | -14269.68 |
% of Exp. Cold Total (secs) | 61.17% | 85.21% | 75.93% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 7 | 65748.00 | 9392.57 |
TE_007AE | 8 | 74427.00 | 9303.37 | |
TE_00B26 | 11 | 104794.00 | 9526.73 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 3 | 28246.00 | 9415.33 |
TE_00CA8 | 1 | 9717.00 | 9717.00 | 4 Chip SI Modes | TE_00C62 | 0 | 0.00 | 0.00 |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 3655600 | 3632800 | 3640400 |
Total Actual Time (secs) | 4003154 | 3920143 | 4040176 |
Delta From Expected (secs) | 347554.52 | 287343.04 | 399776.65 |
% of Expected Total (secs) | 109.51% | 107.91% | 110.98% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 2193360.0 | 2179680.0 | 2184240.0 |
Total Actual Cold Time (secs) | 1994254 | 1943328 | 1894676 |
Delta From Expected (secs) | -199105.79 | -236351.64 | -289563.27 |
% of Exp. Cold Total (secs) | 90.92% | 89.16% | 86.74% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 477 | 3935842.52 | 8251.24 |
TE_007AE | 475 | 3894616.04 | 8199.19 | |
TE_00B26 | 474 | 3887783.93 | 8202.08 | Old 6 Chip SI Modes | TE_00216 | 5 | 478338.25 | 95667.65 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 6 | 52178.00 | 8696.33 |
TE_00CA8 | 3 | 25527.00 | 8509.00 | 4 Chip SI Modes | TE_00C62 | 3 | 167526.73 | 55842.24 |
A word about the COLD Time stats:
- The Total Expected Cold Time value in the table below is 60.0% of the Total Expected Time (see Table above).
- Total Actual Cold Time is the sum of all time during each measurement where the temperature was <= -118.7 degrees C
- % of Expected Total is the fraction of the Total Expected Time achieved
SI Mode Mapping between 6,5 and 4 chip modes:
The 6 chip SI Modes consist of three distinct modes. But there are only 2, 5 chip SI Modes and only one 4 chip SI mode. To make tracking feasible, the 4 and 5 chip modes were mapped into the 6 chip modes in the following manner:
6 chip 5 chip 4 chip
TE_007AC -> TE_00C60 TE_00C62
TE_00B26 -> TE_00C60 TE_00C62
TE_007AE -> TE_00CA8
All of the TE_00CA8s get counted as TE_007AE
Half of the TE_00C60s get counted towards TE_007AC and the other half get counted with the TE_00B26s
Half of the TE_00C62s get counted towards TE_007AC and the other half get counted with the TE_00B26s.
So watchout for TE_00B26 over-representation.
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