The present targets for the Total and Cold times are:
Total time per SI Mode per measurement: 7600.0 seconds
Fraction of total time the measurement should be cold: 60.0%
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Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 60800 | 45600 | 68400 |
Total Actual Time (secs) | 64445 | 43036 | 66526 |
Delta From Expected (secs) | 3645.00 | -2564.00 | -1874.00 |
% of Expected Total (secs) | 106.00% | 94.38% | 97.26% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 36480.0 | 27360.0 | 41040.0 |
Total Actual Cold Time (secs) | 29408 | 9360 | 29147 |
Delta From Expected (secs) | -7071.98 | -17999.44 | -11892.07 |
% of Exp. Cold Total (secs) | 80.61% | 34.21% | 71.02% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 8 | 64445.00 | 8055.63 |
TE_007AE | 6 | 43036.00 | 7172.67 | |
TE_00B26 | 9 | 66526.00 | 7391.78 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 0 | 0.00 | 0.00 |
TE_00CA8 | 0 | 0.00 | 0.00 | 4 Chip SI Modes | TE_00C62 | 0 | 0.00 | 0.00 |
III. Statistics Since the Start of the Current Epoch
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 129200 | 114000 | 152000 |
Total Actual Time (secs) | 122257 | 102501 | 167480 |
Delta From Expected (secs) | -6943.00 | -11499.00 | 15480.23 |
% of Expected Total (secs) | 94.63% | 89.91% | 110.18% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 77520.0 | 68400.0 | 91200.0 |
Total Actual Cold Time (secs) | 69164 | 35068 | 94527 |
Delta From Expected (secs) | -8355.56 | -33331.93 | 3327.04 |
% of Exp. Cold Total (secs) | 89.22% | 51.27% | 103.65% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 17 | 122257.00 | 7191.59 |
TE_007AE | 14 | 96408.00 | 6886.29 | |
TE_00B26 | 18 | 125058.00 | 6947.67 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 1 | 7532.00 | 7532.00 |
TE_00CA8 | 1 | 6093.00 | 6093.00 | 4 Chip SI Modes | TE_00C62 | 1 | 34890.23 | 34890.23 |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 3549200 | 3526400 | 3503600 |
Total Actual Time (secs) | 3884786 | 3793685 | 3878257 |
Delta From Expected (secs) | 335586.52 | 267285.04 | 374657.65 |
% of Expected Total (secs) | 109.46% | 107.58% | 110.69% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 2129520.0 | 2115840.0 | 2102160.0 |
Total Actual Cold Time (secs) | 1938090 | 1889659 | 1832405 |
Delta From Expected (secs) | -191429.39 | -226180.64 | -269754.84 |
% of Exp. Cold Total (secs) | 91.01% | 89.31% | 87.17% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 465 | 3831509.52 | 8239.81 |
TE_007AE | 462 | 3777875.04 | 8177.22 | |
TE_00B26 | 457 | 3740075.93 | 8183.97 | Old 6 Chip SI Modes | TE_00216 | 5 | 478338.25 | 95667.65 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 3 | 23932.00 | 7977.33 |
TE_00CA8 | 2 | 15810.00 | 7905.00 | 4 Chip SI Modes | TE_00C62 | 3 | 167526.73 | 55842.24 |
A word about the COLD Time stats:
- The Total Expected Cold Time value in the table below is 60.0% of the Total Expected Time (see Table above).
- Total Actual Cold Time is the sum of all time during each measurement where the temperature was <= -118.7 degrees C
- % of Expected Total is the fraction of the Total Expected Time achieved
SI Mode Mapping between 6,5 and 4 chip modes:
The 6 chip SI Modes consist of three distinct modes. But there are only 2, 5 chip SI Modes and only one 4 chip SI mode. To make tracking feasible, the 4 and 5 chip modes were mapped into the 6 chip modes in the following manner:
6 chip 5 chip 4 chip
TE_007AC -> TE_00C60 TE_00C62
TE_00B26 -> TE_00C60 TE_00C62
TE_007AE -> TE_00CA8
All of the TE_00CA8s get counted as TE_007AE
Half of the TE_00C60s get counted towards TE_007AC and the other half get counted with the TE_00B26s
Half of the TE_00C62s get counted towards TE_007AC and the other half get counted with the TE_00B26s.
So watchout for TE_00B26 over-representation.
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