The present targets for the Total and Cold times are:
Total time per SI Mode per measurement: 7600.0 seconds
Fraction of total time the measurement should be cold: 60.0%
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Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 60800 | 53200 | 60800 |
Total Actual Time (secs) | 59206 | 53019 | 61047 |
Delta From Expected (secs) | -1594.00 | -181.00 | 247.00 |
% of Expected Total (secs) | 97.38% | 99.66% | 100.41% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 36480.0 | 31920.0 | 36480.0 |
Total Actual Cold Time (secs) | 29662 | 18350 | 30979 |
Delta From Expected (secs) | -6817.52 | -13569.17 | -5500.65 |
% of Exp. Cold Total (secs) | 81.31% | 57.49% | 84.92% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 8 | 59206.00 | 7400.75 |
TE_007AE | 7 | 53019.00 | 7574.14 | |
TE_00B26 | 8 | 61047.00 | 7630.88 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 0 | 0.00 | 0.00 |
TE_00CA8 | 0 | 0.00 | 0.00 | 4 Chip SI Modes | TE_00C62 | 0 | 0.00 | 0.00 |
III. Statistics Since the Start of the Current Epoch
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 152000 | 136800 | 174800 |
Total Actual Time (secs) | 141408 | 126652 | 187674 |
Delta From Expected (secs) | -10592.00 | -10148.00 | 12874.23 |
% of Expected Total (secs) | 93.03% | 92.58% | 107.37% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 91200.0 | 82080.0 | 104880.0 |
Total Actual Cold Time (secs) | 73857 | 44058 | 104904 |
Delta From Expected (secs) | -17342.85 | -38021.65 | 24.40 |
% of Exp. Cold Total (secs) | 80.98% | 53.68% | 100.02% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 20 | 141408.00 | 7070.40 |
TE_007AE | 17 | 120559.00 | 7091.71 | |
TE_00B26 | 21 | 145252.00 | 6916.76 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 1 | 7532.00 | 7532.00 |
TE_00CA8 | 1 | 6093.00 | 6093.00 | 4 Chip SI Modes | TE_00C62 | 1 | 34890.23 | 34890.23 |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 3572000 | 3549200 | 3526400 |
Total Actual Time (secs) | 3903937 | 3817836 | 3898451 |
Delta From Expected (secs) | 331937.52 | 268636.04 | 372051.65 |
% of Expected Total (secs) | 109.29% | 107.57% | 110.55% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 2143200.0 | 2129520.0 | 2115840.0 |
Total Actual Cold Time (secs) | 1942783 | 1898649 | 1842782 |
Delta From Expected (secs) | -200416.69 | -230870.37 | -273057.48 |
% of Exp. Cold Total (secs) | 90.65% | 89.16% | 87.09% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 468 | 3850660.52 | 8227.91 |
TE_007AE | 465 | 3802026.04 | 8176.40 | |
TE_00B26 | 460 | 3760269.93 | 8174.50 | Old 6 Chip SI Modes | TE_00216 | 5 | 478338.25 | 95667.65 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 3 | 23932.00 | 7977.33 |
TE_00CA8 | 2 | 15810.00 | 7905.00 | 4 Chip SI Modes | TE_00C62 | 3 | 167526.73 | 55842.24 |
A word about the COLD Time stats:
- The Total Expected Cold Time value in the table below is 60.0% of the Total Expected Time (see Table above).
- Total Actual Cold Time is the sum of all time during each measurement where the temperature was <= -118.7 degrees C
- % of Expected Total is the fraction of the Total Expected Time achieved
SI Mode Mapping between 6,5 and 4 chip modes:
The 6 chip SI Modes consist of three distinct modes. But there are only 2, 5 chip SI Modes and only one 4 chip SI mode. To make tracking feasible, the 4 and 5 chip modes were mapped into the 6 chip modes in the following manner:
6 chip 5 chip 4 chip
TE_007AC -> TE_00C60 TE_00C62
TE_00B26 -> TE_00C60 TE_00C62
TE_007AE -> TE_00CA8
All of the TE_00CA8s get counted as TE_007AE
Half of the TE_00C60s get counted towards TE_007AC and the other half get counted with the TE_00B26s
Half of the TE_00C62s get counted towards TE_007AC and the other half get counted with the TE_00B26s.
So watchout for TE_00B26 over-representation.
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