The present targets for the Total and Cold times are:
Total time per SI Mode per measurement: 7600.0 seconds
Fraction of total time the measurement should be cold: 60.0%
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Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 60800 | 45600 | 60800 |
Total Actual Time (secs) | 59206 | 47031 | 59097 |
Delta From Expected (secs) | -1594.00 | 1431.00 | -1703.00 |
% of Expected Total (secs) | 97.38% | 103.14% | 97.20% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 36480.0 | 27360.0 | 36480.0 |
Total Actual Cold Time (secs) | 42131 | 13657 | 25966 |
Delta From Expected (secs) | 5651.09 | -13702.64 | -10513.93 |
% of Exp. Cold Total (secs) | 115.49% | 49.92% | 71.18% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 8 | 59206.00 | 7400.75 |
TE_007AE | 6 | 47031.00 | 7838.50 | |
TE_00B26 | 8 | 59097.00 | 7387.12 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 0 | 0.00 | 0.00 |
TE_00CA8 | 0 | 0.00 | 0.00 | 4 Chip SI Modes | TE_00C62 | 0 | 0.00 | 0.00 |
III. Statistics Since the Start of the Current Epoch
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 167200 | 144400 | 190000 |
Total Actual Time (secs) | 160842 | 135098 | 202108 |
Delta From Expected (secs) | -6358.00 | -9302.00 | 12108.23 |
% of Expected Total (secs) | 96.20% | 93.56% | 106.37% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 100320.0 | 86640.0 | 114000.0 |
Total Actual Cold Time (secs) | 95484 | 44058 | 109568 |
Delta From Expected (secs) | -4835.35 | -42581.65 | -4431.34 |
% of Exp. Cold Total (secs) | 95.18% | 50.85% | 96.11% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 22 | 160842.00 | 7311.00 |
TE_007AE | 18 | 129005.00 | 7166.94 | |
TE_00B26 | 23 | 159686.00 | 6942.87 | Old 6 Chip SI Modes | TE_00216 | 0 | 0.00 | 0.00 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 1 | 7532.00 | 7532.00 |
TE_00CA8 | 1 | 6093.00 | 6093.00 | 4 Chip SI Modes | TE_00C62 | 1 | 34890.23 | 34890.23 |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Expected Time (secs) | 3587200 | 3556800 | 3541600 |
Total Actual Time (secs) | 3923371 | 3826282 | 3912885 |
Delta From Expected (secs) | 336171.52 | 269482.04 | 371285.65 |
% of Expected Total (secs) | 109.37% | 107.58% | 110.48% |
Stats | TE_007AC | TE_007AE | TE_00B26 |
---|---|---|---|
Total Exp. Cold Time (secs) | 2152320.0 | 2134080.0 | 2124960.0 |
Total Actual Cold Time (secs) | 1964410 | 1898649 | 1847446 |
Delta From Expected (secs) | -187909.18 | -235430.37 | -277513.22 |
% of Exp. Cold Total (secs) | 91.27% | 88.97% | 86.94% |
SI Mode | Total Number of Obs. | Total Exposure Time (sec) | Average Exposure (sec/obs) | |
---|---|---|---|---|
Primary 6 Chip SI Modes | TE_007AC | 470 | 3870094.52 | 8234.24 |
TE_007AE | 466 | 3810472.04 | 8176.98 | |
TE_00B26 | 462 | 3774703.93 | 8170.35 | Old 6 Chip SI Modes | TE_00216 | 5 | 478338.25 | 95667.65 |
TE_0021C | 0 | 0.00 | 0.00 | |
TE_008EA | 0 | 0.00 | 0.00 | 5 Chip SI Modes | TE_00C60 | 3 | 23932.00 | 7977.33 |
TE_00CA8 | 2 | 15810.00 | 7905.00 | 4 Chip SI Modes | TE_00C62 | 3 | 167526.73 | 55842.24 |
A word about the COLD Time stats:
- The Total Expected Cold Time value in the table below is 60.0% of the Total Expected Time (see Table above).
- Total Actual Cold Time is the sum of all time during each measurement where the temperature was <= -118.7 degrees C
- % of Expected Total is the fraction of the Total Expected Time achieved
SI Mode Mapping between 6,5 and 4 chip modes:
The 6 chip SI Modes consist of three distinct modes. But there are only 2, 5 chip SI Modes and only one 4 chip SI mode. To make tracking feasible, the 4 and 5 chip modes were mapped into the 6 chip modes in the following manner:
6 chip 5 chip 4 chip
TE_007AC -> TE_00C60 TE_00C62
TE_00B26 -> TE_00C60 TE_00C62
TE_007AE -> TE_00CA8
All of the TE_00CA8s get counted as TE_007AE
Half of the TE_00C60s get counted towards TE_007AC and the other half get counted with the TE_00B26s
Half of the TE_00C62s get counted towards TE_007AC and the other half get counted with the TE_00B26s.
So watchout for TE_00B26 over-representation.
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