ECS Measurement SI Mode Trends



Statistics Run Date: 2020Jul20

  1. Introduction
  2. Since Start of Current Epoch
  3. THE RULES
  4. Important Notes

I. Introduction

 This web page will help you track ECS measurement performance with regard to
total and cold time on each of the ECS SI modes as well as individual chips.

Cold time is defined as any temerature reading <= -119.2 degrees C.

We are operating on 6 month epochs. The epochs start on the following Days of the Year:

DOY 032 and DOY 213.

The present epoch begins at: 2020:032:00:00:00.00 and today is: 2020:202:19:51:11.627 .

It is important to note that the target exposure times listed below will increase by a factor
of 12% every 6 month epoch due to the half-life of the calibration source.

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II. Statistics Since the Start of the Current Epoch

Cold Time Statistics:

ACIS Chip Set Cold Time
Chip Required (seconds) Achieved (seconds)
I0 130000 96728.74
I1 130000 150434.13
I2 130000 150434.13
I3 130000 150434.13
S0 - 62482.74
S1 - 94245.7
S2 - 127448.52
S3 170000 212916.87
S4 - 62482.74
S5 - 62482.74





Total Time Statistics:

Total ECS Time:

ECS Trending Table: Total Time
Stats TE_007AC TE_007AE TE_00B26
Total Exp. Cold Time (secs) 189999 189999 189999
Total Actual Cold Time (secs) 64965 62482 85468
Delta From Expected (secs) -125033 -127516 -104530
% of Exp. Cold Total (secs) 34.19% 32.89% 44.98%

ECS Trending Table: SI Mode Stats
SI Mode Total Number of Obs. Total Exposure Time (sec) Average Exposure (sec/obs)
Primary 6 Chip SI Modes
TE_007AC 38 301676.00 7938.84
TE_007AE 37 264496.94 7148.57
TE_00B26 29 196485.71 6775.37
Old 6 Chip SI Modes
TE_00216 0 0.00 0.00
TE_0021C 0 0.00 0.00
TE_008EA 0 0.00 0.00
5 Chip SI Modes
TE_00C60 11 104297.00 9481.55
TE_00CA8 3 28941.00 9647.00
4 Chip SI Modes
TE_00C62 7 151270.00 21610.00
Totals: 125 1047166.65 8377.33
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Important Notes:

The Rules:

The rules to be followed are:

Rule #1: The key time period for balancing SI mode statistics is the 6 month Epoch
         By the end of the epoch, the SI mode statistics should match the rules stated below.

Rule #2: Each of the three, default, 6 chip, SI modes (or their 5 chip equivalents) must be used
         at least once in each load week.

           - If two SI modes are lagging in either cold time or total time, apportion the week's ECS
             measurements between the two of them roughly commensurate with the amount they are lagging.

           - The 6 month Epoch allows "even" correction of two lagging SI modes. No
             need to pile a weeks worth of ECS measurements on one SI mode if two are lagging.

Rule #3: Make certain to spread the amount of COLD ECS time as evenly as possible across all three SI modes
         Balance Cold measurement data between the three default 6-chip modes within 10%
         of each other on an Epoch basis


Rule #4: Spread the amount of *Total* ECS time as evenly as possible across all three SI modes. 

                 - Balance Total measurement data between the three default 6-chip modes within 10%
                   of each other on an Epoch basis.


         Rule #3 takes precedence over Rule #4.   


Rule #5:At least 60% of scheduled ECS measurement time must be -119.2 deg. C


Rule #6: Any ECS measurements during a Perigee Passage that are cold MUST be assigned to the nominal
         ECS run SI modes. i.e. Any requested Rawmode runs can be done with a warm focal plane.


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A word about the Total Time stats:

    - The Total Expected Time values for each SI mode in the table is calculated by:

        # of ECS runs executed in this epoch so far * 10,000.0 * 0.76 / 3.0

    Where:

         10,000.0 seconds is the maximum possible time for ECS runs

         We exepct only 7600.0 seconds on average - hence multiply by 0.76

         We divide by three because we want the time evenly distributed across all three aggregate SI modes

A word about the COLD Time stats:

    Cold Time is defiined by focal plane temperatures <= -119.2 degrees C:

     The Total Expected Cold Time value is 60.0% of the Total Expected Time (see above).

SI Mode Mapping between 6,5 and 4 chip modes:

    The 6 chip SI Modes consist of three distinct modes. But there are only 2, 5 chip SI Modes and only one 4 chip SI mode. To make tracking feasible, the 4 and 5 chip modes were mapped into the 6 chip modes in the following manner:

       6 chip               5 chip         4 chip

    TE_007AC -> TE_00C60 TE_00C62

    TE_00B26 -> TE_00C60 TE_00C62

    TE_007AE -> TE_00CA8

All of the TE_00CA8s get counted as TE_007AE

Half of the TE_00C60s get counted towards TE_007AC and the other half get counted with the TE_00B26s

Half of the TE_00C62s get counted towards TE_007AC and the other half get counted with the TE_00B26s.

So watchout for TE_00B26 over-representation.

SI Mode to Chip Mappings:

    TE_007AC -> I0 - I3, S2, S3

    TE_007AE -> S0 - S5

    TE_00B26 -> I0 - I3, S1, S3

    TE_00C60 -> I0 - I3, S3

    TE_00C62 -> I1 - I3, S3

    TE_00CA8 -> S1 - S5



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